Field of the Invention
The present invention relates to an image capture apparatus and a control method thereof.
Description of the Related Art
An analog-to-digital converter (A/D converter), for example, is implemented in some solid-state image sensors (hereinafter, simply referred to as image sensors) such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
In the case where an A/D converter is implemented in an image sensor in which a plurality of pixels are arranged two-dimensionally in row and column directions, a configuration is known in which an A/D converter is provided for each pixel column (a column-parallel or column A/D conversion architecture). In the column-parallel A/D conversion architecture, the conversion rate of each A/D converter can be reduced to a row read-out rate, and therefore, this architecture contributes to a reduction in power consumption of the image sensor as well as an increase in the read-out rate of the image sensor.
A configuration is known in which a ramp A/D converter is used in the column-parallel A/D conversion architecture (refer to Japanese Patent Laid-Open No. 2013-9087). The ramp A/D converter obtains, as an A/D conversion result, a digital value corresponding to a time required for a ramp signal voltage, whose voltage value increases at a constant rate over time, to increase from an initial value and exceed an analog voltage that is to be subjected to A/D conversion. The digital value can be obtained by counting pulse signals having a constant frequency using a counter, for example.
In principle, the larger the value to be converted is, or the higher the resolution of A/D conversion is, the longer it takes for the ramp A/D converter to perform A/D conversion. Therefore, Japanese Patent Laid-Open No. 2013-9087 discloses a configuration in which the A/D conversion time for a large value is reduced by making the increase rate of the ramp signal larger in the case where the pixel signal level is greater than a threshold value than in the case where the pixel signal level is smaller than the threshold value.
However, increasing the increase rate of the ramp signal means decreasing the resolution of A/D conversion. Therefore, in the configuration described in Japanese Patent Laid-Open No. 2013-9087, particularly in the case where a digital gain is applied after A/D conversion, discernible degradation in image quality may occur regarding high level pixel signals.